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MulticoreA multicore processor is a chip with more than one processing units (cores). Mostly, each unit can run multiple instructions at the same time and each has its own cache. The limitations of single-processor architecture - Narrow data bandwidth, big gap between CPU speed and memory speed: It is reported that on average, 75% of CPU time is wasted in waiting for memory access results.
- High frequency has a ultimate size limit: at light speed, a 100GHz chip can only be in size of 3 mm.
- long pipeline introduces big penalty for mis-prediction/wrong speculation
- High energy consumption and hard to cool off
- Bad cost/performance ratio
Multicore architecture is a solution A multicore architecture is actually a SMP implemented on a single VLSI integrated circuit. The goal is to allow greater utilization of thread-level parallelism (TLP), especially for applications that lack sufficient instruction-level parallelism (ILP) to make good use of superscalar processors. It is called Chip-level multiprocessing (also known as CMP), or Chip Multithreading (CMT) The characteristics of a CMP system - A slow but wide approach: improve the throughput of the whole computer system.
- Good for transaction processing, database and scientific computing applications.
- No benefits for single application that cannot be parallelized (divided and run on several tasks or threads)
- Better data locality than regular multi-processor architectures
- Better communication between processing units
- saves space, save energy.
- better cost/performance ratio than single-core processor
Example multicore processors The whole microprocessor industry is jumping into multicore today. The latest versions of most RISC architectures use CMP, including Other microprocessor families are also expected to use CMP in future versions. - Intel's Itanium is expected to do so in the second half of 2005, with a release codenamed Montecito; then even more extensively in 2007 with a product codenamed Tukwila.
- Intel's Pentium is expected to start using CMP in 2006
- AMD's Opteron is expected to incorporate the technique in mid-2005.
See also
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