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Mpc5xxThe MPC5xx family of processors such as the MPC555 and MPC565 are 32-bit PowerPC embedded microprocessors that operate between 40 and 66 MHz and are frequently used in automotive applications including as engine and transmission controllers. They are generally considered microcontrollers because of their integrated peripheral set and their unique architecture: no MMU, large on-chip SRAM and very large (as much as 1 Megabyte) low latency access on-chip Flash memories, which means their archtecture is tailored to control applications. The peripherals on each model vary, but frequently include analog to digital converters (QADC), Time Processor Unit (TPU), GPIO, and UARTS/serial (QSMCM). The MPC5xx family descends from the 8xx (PowerQUICC) family core, which means it is a Harvard architecture, single issue core. Unlike the 8xx family, the 5xx variants have a floating point unit. While some of the earlier chips like the MPC509 had an instruction cache, the recent chips have the capability to contain large ammounts of NOR Flash memory on-board which is capable of bursting instructions to the processor. Some low cost chips omit the flash memory because it adds a lot of die area, driving up the price of the chip. Many controller applications run very long control loops where there is not a large dataset and low latency,deterministic access to both data and instruction routines is more important. If most of the data can be stored in the on-chip SRAM available to the datapath of the processor in a single cylce, performance can be quite good. If data must be accessed off-chip frequently, performance can be quite poor because the chip cannot burst data accesses from external RAM and has a very slow bus access protocol. Because of the simple memory interface that can be programmed by setting a default memory location and writing a few base registers, the chips are quite popular with hobbiysts as well as with automotive and industrial developers.
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