Montecito

• Two cores per die
• 2-way coarse-grained multithreading per core (not simultaneous). Montecito-flavour of multi-threading is dubbed temporal, or TMT. The two seperate threads do not run simultaneously, but the core switches thread in case of a high latency event, like an L3 cache miss which would otherwise stall execution. By this technique, database-like workloads should improve by 15-35 %.
• a total of 4 threads per die
• separate 1 MB Instruction L2 and 256 KB Data L2 per core, improved hierarchy
• 24 MB L3 per die
• 1.72 billion transistors per die, which is added up from core logic - 57M, or 28,5M per core // core caches - 106.5M // 24 MB L3 cache - 1550M // bus logic & I/O - 6.7M
• Die size is said to be 596 mm²
• Clock speeds between 2.0GHz and 2.5GHz (dynamically variable/top-of-the-line model). 2.5 GHz is the maximum Montecito's design is validated for, but it's more likely that it will top out around 2.2 GHz actually.
• Advanced clock scaling technology for power management -- the clock rate is not fixed, but adjusted to the power envelope (100 W), what means that under some usage patterns -- so called low activity workloads which generate less heat while being executed -- the chip will be able to scale up and adjust core voltage (while under worst case condition, like excessive ambient temperature or broken down fans, it _might_ be able to scale down clock speeds and voltage). Low-activity workloads are rather integer-intensive computations, mostly commercial, database applications. They should be boosted by around a factor of 10 %. This is Foxton technology. Foxton's clock scaling can be disabled if required.
• Lower power consumption and thermal dissipation than earlier flagship Itaniums, despite the high transistor count and higher clock speeds. 100 W has been suggested. This is mainly achieved by applying different types of transistors. By default, slower and low-leakage transistor were used, while high-speed, thus high-leakage ones where it was necessary.
• Advanced compensation for errors in cache, for reliable operation under mission-critical workloads. This is Pellston technology.
• Virtualization technology allowing multiple OS instances per chip. This is Silvervale technology.
• Improved, higher bandwidth front side bus (FSB), with three times the capacity of the existing bus design. What we don't know yet is whether it meant to be at device level (per die) or at system level (per node, with 4 dies). System throughput per node will be at least 21 Gbytes per second.
• Will also be avaliable with legacy FSB for upgrading existing system designs
• 90 nanometers design with 65 nm shrink planned (shrink codenamed Montvale, release one year later, tail end of 2006)
• Under evaluation by major OEMs
• Commercial launch: 2005 H2
• Volume: 2006

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